Stage/bijverdienste Product Design student HBO/WO (€400 per maand)

Omschrijving stage

Wil jij een nieuw product ontwerpen voor veelbelovende IoT producten? Van schets tot de daadwerkelijke verkoop? Photoshop, productontwerp, 3d tekenen, en het daadwerkelijk uitvoeren van een demo-behuizing en opzet? Heb jij ervaring met design in 3D, van schets, brochure tot daadwerkelijk demo-model? Dan zoeken wij jou!

De werkzaamheden betreffen het meewerken aan de ontwikkeling van nieuwe IoT sensor producten. Bijvoorbeeld slimme designs voor smart homes en health.

De stage bestaat uit de volgende onderwerpen:

  • Ontwerp en uitvoering van demo-modellen. Wij hebben een aantal werkende sensor oplossingen in de vorm van een ‘kale’, maar werkende sensor. Hiervoor willen wij een aansprekende behuizing die daadwerkelijk in productie kan gaan. Bij voorkeur krijgen wij daarbij een volledig werkende demo-opzet van de sensor.
  • Brochures en presentaties: hierbij verwachten we van jou dat je op basis van de aangeleverde specs pakkende documenten kunt maken inclusief benodigde illustraties
  • Daarnaast wordt je betrokken bij nieuwe project-ideeën

Je verricht de werkzaamheden vanuit huis, wel is er de mogelijkheid voor wekelijks overleg.

Jij

  • Bent student HBO of WO, bijvoorbeeld Industrieel Product Ontwerpen;
  • Bent creatief, maar ook zorgvuldig;
  • Bezit uitstekende 3D ontwerpkwaliteiten, kan mooie, daadwerkelijk werkende demo- modellen maken en kan daarnaast pakkende presentaties en brochures ontwerpen;
  • Je hebt een zelfstandige instelling, maar kunt ook goed samenwerken;
  • Woont bij voorkeur in de omgeving van Nijmegen

Bij voorkeur ben je per direct beschikbaar.

Wij bieden 400 euro op basis van een 40-urige werkweek. De stage is voor 3 maanden.

Mocht je interesse hebben, stuur dan jouw CV en motivatiebrief naar Rene Eekelder (rene.eekelder@advsolned.com)

How to export designed IIR/FIR filters to Matlab

For many IoT sensor measurement applications, an IIR or FIR filter is just one of the many components needed for an algorithm. This could be a powerline interference canceller for a biomedical application or even a simpler DC loadcell filter. In many cases, it is necessary to integrate a filter into a complete algorithm in another domain.

Matlab is a well-established numerical computing language developed by the Mathworks that allows for the design of algorithms, matrix data manipulations and data analysis. The product offers a broad range of algorithms and support functions for signal processing applications, and as such is very popular amongst many scientists and engineers worldwide.

ASN Filter Designer automatic code generator for Matlab

The ASN Filter Designer greatly simplifies exporting a designed filter to Matlab via its automatic code generator. The code generator supports all aspects of the ASN Filter Designer, allowing for a complete design comprised of H1, H2 and H3 filters and math operators to be fully integrated with an algorithm in Matlab.

The Matlab code generator can be accessed via the filter summary options (as shown on the right). Selecting this option will automatically generate a Matlab .m file based on the current design.

In order to use the generated code in Matlab without the need for Signal Processing Toolbox, the following three framework files are provided in the ASN Filter Designer’s \Matlab directory:

ASNFDMatlabFilterData.m
ASNFDMatlabImport.m
ASNFDFilter.m

These framework files do not have any special Matlab toolbox dependences, and the example script ASNFDMatlabDemo.m demonstrates the simplicity with which the framework can be integrated into your application for your designed filter. Several example filters generated via the automatic code generator are given within ASNFDMatlabDemo.m in order to get you going!

Comparing the results to Matlab’s Signal Processing Toolbox

It’s sometimes informative to compare the results of the ASN Filter Designer’s DSP library functions to that of Matlab’s Signal Processing Toolbox.

Designing an IIR Chebyshev Type I filter with the following specifications:

Fs: 500Hz
Passband frequency: 0-25Hz
Type: Lowpass
Method: Chebyshev Type I
Stopband attenuation @ 125Hz: ≥ 80 dB
Passband ripple: ≤ 0.1dB
Order: 5

Graphically entering the specifications into the ASN Filter Designer, and fine tuning the design marker positions, the tool automatically designs the filter as a Biquad cascade. Notice that the tool automatically finds the required filter order, and in essence – automatically produces the filter’s exact technical specification!

The frequency response of a 5th order IIR Chebyshev Type I lowpass filter meeting the specifications is shown below:

The resulting filter coefficients are:

Designing the same filter in Matlab using Signal Processing Toolbox:

Fs=500;
Rp=0.1;
Rs=80;
F=2*[25,125]/Fs;

[N,Wn]=cheb1ord(F(1),F(2),Rp,Rs)
[z, p, k] = cheby1(N,Rp,Wn,'low'); % design lowpass

[sos,g]=zp2sos(z,p,k,'up')  % generate SOS form

Running the script, we get the following, where each row of sos is a biquad arranged as: b0 b1 b2 a0 a1 a2

Analysing both sets of numerator and denominator coefficients, we get exactly the same result! But what about the gain? Matlab outputs a net gain, g = 3.0096e-05 but the ASN Filter Designer optimally assigns a gain to each biquad. Thus, combining the biquad section gains, i.e. 0.078643, 0.013823 and 0.027685 results in a net gain of 3.0096e-05, which is exactly the same net gain as Matlab!

Conclusion: the ASN Filter Designer’s DSP IIR library functions completely match Matlab’s Signal Processing Toolbox results!!

The complete automatically generated code is shown below, where it can be seen that the biquad gains have been pre-multiplied with the feedforward coefficients.

Using the generated code with Signal Processing Toolbox

If you have Signal Processing Toolbox installed, then you may directly use the generated coefficients given in SOS with the sosfilt() command, e.g.

Clear all;

ASNFD_SOS=[ 0.07864301814, 0.07864301814, 0.00000000000, 1.00000000000,-0.84271396371, 0.00000000000;...
 0.01382289248, 0.02764578495, 0.01382289248, 1.00000000000,-1.70536517618, 0.76065674608;...
 0.02768538360, 0.05537076720, 0.02768538360, 1.00000000000,-1.79181447713, 0.90255601154;...
];
  
y=sosfilt(ASNFD_SOS, x); %  x is your input data

plot(x,y); % plot results

As seen, it is as simple as copying and pasting the filter coefficients from the ASN Filter Designer’s filter summary into a Matlab script.

 

 

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Implementing Biquad IIR filters with the ASN Filter Designer and the Arm CMSIS-DSP software framework

Infinite impulse response (IIR) filters are useful for a variety of sensor measurement applications, including measurement noise removal and unwanted component cancellation, such as powerline interference. Although several practical implementations for the IIR exist, the Direct form II Transposed structure offers the best numerical accuracy for floating point implementation. However, when considering fixed point implementation on a microcontroller, the Direct Form I structure is considered to be the best choice by virtue of its large accumulator that accommodates any intermediate overflows.

This application note specifically addresses IIR biquad filter design and implementation on a Cortex-M based microcontroller with the ASN Filter Designer for both floating point and fixed point applications via the Arm CMSIS-DSP software framework. Details are also given (including a reference example project) regarding implementation of the IIR filter in Arm/Keil’s MDK industry standard Cortex-M microcontroller development kit.

Introduction

ASN Filter Designer provides engineers with a powerful DSP experimentation platform, allowing for the design, experimentation and deployment of complex IIR and FIR (finite impulse response) digital filter designs for a variety of sensor measurement applications. The tool’s advanced functionality, includes a graphical based real-time filter designer, multiple filter blocks, various mathematical I/O blocks, live symbolic math scripting and real-time signal analysis (via a built-in signal analyser). These advantages coupled with automatic documentation and code generation functionality allow engineers to design and validate a digital filter within minutes rather than hours.

The Arm CMSIS-DSP (Cortex Microcontroller Software Interface Standard) software framework is a rich collection of over sixty DSP functions (including various mathematical functions, such as sine and cosine; IIR/FIR filtering functions, complex math functions, and data types) developed by Arm that have been optimised for their range of Cortex-M processor cores. The framework makes extensive use of highly optimised SIMD (single instruction, multiple data) instructions, that perform multiple identical operations in a single cycle instruction. The SIMD instructions (if supported by the core) coupled together with other optimisations allow engineers to produce highly optimised signal processing applications for Cortex-M based micro-controllers quickly and simply.

ASN Filter Designer fully supports the CMSIS-DSP software framework, by automatically producing optimised C code based on the framework’s DSP functions via its code generation engine.

Designing IIR filters with the ASN Filter Designer

ASN Filter Designer provides engineers with an easy to use, intuitive graphical design development platform for both IIR and FIR digital filter design. The tool’s real-time design paradigm makes use of graphical design markers, allowing designers to simply draw and modify their magnitude frequency response requirements in real-time while allowing the tool automatically fill in the exact specifications for them.

Consider the design of the following technical specification:

Fs:   500Hz
Passband frequency:   0-40Hz
Type:   Lowpass
Method:   Elliptic
Stopband attenuation @ 125Hz:   ≥ 80 dB
Passband ripple:   < 0.1dB
Order:   Small as possible

Graphically entering the specifications into the ASN Filter Designer, and fine tuning the design marker positions, the tool automatically designs the filter as a Biquad cascade (this terminology will be discussed in the following sections), automatically choosing the required filter order, and in essence – automatically producing the filter’s exact technical specification!

The frequency response of a 5th order IIR Elliptic Lowpass filter meeting the specifications is shown below:

This 5th order Lowpass filter will form the basis of the discussion presented herein.

Biquad IIR filters

The IIR filter implementation discussed herein is said to be biquad, since it has two poles and two zeros as illustrated below in Figure 1. The biquad implementation is particularly useful for fixed point implementations, as the effects of quantization and numerical stability are minimised. However, the overall success of any biquad implementation is dependent upon the available number precision, which must be sufficient enough in order to ensure that the quantised poles are always inside the unit circle.

Figure 1: Direct Form I (biquad) IIR filter realization and transfer function.

Analysing Figure 1, it can be seen that the biquad structure is actually comprised of two feedback paths (scaled by \(a_1\) and \(a_2\)), three feed forward paths (scaled by \(b_0, b_1\) and \(b_2\)) and a section gain, \(K\). Thus, the filtering operation of Figure 1 can be summarised by the following simple recursive equation:

\(\displaystyle y(n)=K\times\Big[b_0 x(n) + b_1 x(n-1) + b_2 x(n-2)\Big] – a_1 y(n-1)-a_2 y(n-2)\)

Analysing the equation, notice that the biquad implementation only requires four additions (requiring only one accumulator) and five multiplications, which can be easily accommodated on any Cortex-M microcontroller. The section gain, \(K\) may also be pre-multiplied with the forward path coefficients before implementation.

A collection of Biquad filters is referred to as a Biquad Cascade, as illustrated below.

The ASN Filter Designer can design and implement a cascade of up to 50 biquads (Professional edition only).

Floating point implementation

When implementing a filter in floating point (i.e. using double or single precision arithmetic) Direct Form II structures are considered to be a better choice than the Direct Form I structure. The Direct Form II Transposed structure is considered the most numerically accurate for floating point implementation, as the undesirable effects of numerical swamping are minimised as seen by analysing the difference equations.

Figure 2 – Direct Form II Transposed strucutre, transfer function and difference equations

The filter summary (shown in Figure 3) provides the designer with a detailed overview of the designed filter, including a detailed summary of the technical specifications and the filter coefficients, which presents a quick and simple route to documenting your design.

The ASN Filter Designer supports the design and implementation of both single section and Biquad (default setting) IIR filters. However, as the CMSIS-DSP framework does not directly support single section IIR filters, this feature will not be covered in this application note.

The CMSIS-DSP software framework implementation requires sign inversion (i.e. flipping the sign) of the feedback coefficients. In order to accommodate this, the tool’s automatic code generation engine automatically flips the sign of the feedback coefficients as required. In this case, the set of difference equations become,

\(y(n)=b_0 x(n)+w_1 (n-1)\)
\(w_1 (n)= b_1 x(n)+a_1 y(n)+w_2 (n-1)\)
\(w_2 (n)= b_2 x(n)+a_2 y(n)\)

Figure 3: ASN filter designer: filter summary.

 

Automatic code generation to Arm processor cores via CMSIS-DSP

The ASN Filter Designer’s automatic code generation engine facilitates the export of a designed filter to Cortex-M Arm based processors via the CMSIS-DSP software framework. The tool’s built-in analytics and help functions assist the designer in successfully configuring the design for deployment.

All floating point IIR filters designs must be based on Single Precision arithmetic and either a Direct Form I or Direct Form II Transposed filter structure. As discussed in the previous section, the Direct Form II Transposed structure is advocated for floating point implementation by virtue of its higher numerically accuracy.

Quantisation and filter structure settings can be found under the Q tab (as shown on the left). Setting Arithmetic to Single Precision and Structure to Direct Form II Transposed and clicking on the Apply button configures the IIR considered herein for the CMSIS-DSP software framework.

Select the Arm CMSIS-DSP framework from the selection box in the filter summary window:

The automatically generated C code based on the CMSIS-DSP framework for direct implementation on an Arm based Cortex-M processor is shown below:

As seen, the automatic code generator generates all initialisation code, scaling and data structures needed to implement the IIR via the CMSIS-DSP library. This code may be directly used in any Cortex-M based development project – a complete Keil MDK example is available on Arm/Keil’s website. Notice that the tool’s code generator produces code for the Cortex-M4 core as default, please refer to the table below for the #define definition required for all supported cores.

ARM_MATH_CM0 Cortex-M0 core. ARM_MATH_CM4 Cortex-M4 core.
ARM_MATH_CM0PLUS Cortex-M0+ core. ARM_MATH_CM7 Cortex-M7 core.
ARM_MATH_CM3 Cortex-M3 core.
ARM_MATH_ARMV8MBL ARMv8M Baseline target (Cortex-M23 core).
ARM_MATH_ARMV8MML ARMv8M Mainline target (Cortex-M33 core).

Automatic code generation of complex coefficient IIR filters is currently not supported.

Implementing the filter in Arm Keil’s MDK

As mentioned in the previous section, the code generated by the Arm CMSIS-DSP code generator may be directly used in any Cortex-M based development project tooling, such as Arm Keil’s industry standard μVision MDK (microcontroller development kit).

A complete μVision example IIR biquad filter project can be downloaded from Keil’s website, and as seen below is as simple as copying and pasting the code and making minor adjustments to the code.

The example project makes use of μVision’s powerful simulation capabilities, allowing for the evaluation of the IIR filter on M0, M3, M4 and M7 cores respectively. As an added bonus, μVision’s logic analyser may also be used, allowing for comparisons between the ASN Filter Designer’s signal analyser and the reality on a Cortex-M core.

Fixed point implementation

As aforementioned, the Direct Form I filter structure is the best choice for fixed point implementation. However, before implementing the difference equation on a fixed point processor, several important data scaling considerations must be taken into account. As the CMSIS-DSP framework only supports Q15 and Q31 data types for IIR filters, the following discussion relates to an implementation on a 16-bit word architecture, i.e. Q15.

Quantisation

In order to correctly represent the coefficients and input/output numbers, the system word length (16-bit for the purposes of this application note) is first split up into its number of integers and fractional components. The general format is given by:

Q Num of Integers.Fraction length

If we assume that all of data values lie within a maximum/minimum range of \(\pm 1\), we can use Q0.15 format to represent all of the numbers respectively. Notice that Q0.15 (or simply Q15) format represents a maximum of \(\displaystyle 1-2^{-15}=0.9999=0x7FFF\) and a minimum of \(-1=0x8000\) (two’s complement format).

The ASN Filter Designer may be configured for Fixed Point Q15 arithmetic by setting the Word length and Fractional length specifications in the Q Tab (see the configuration section for the details). However, one obvious problem that manifests itself for Biquads is the number range of the coefficients. As poles can be placed anywhere inside the unit circle, the resulting polynomial needed for implementation will often be in the range \(\pm 2\), which would require Q14 arithmetic. In order to overcome this issue, all numerator and denominator coefficients are scaled via a biquad Post Scaling Factor as discussed below.

Post Scaling Factor

In order to ensure that coefficients fit within the Word length and Fractional length specifications, all IIR filters include a Post Scaling Factor, which scales the numerator and denominator coefficients accordingly. As a consequence of this scaling, the Post Scaling Factor must be included within the filter structure in order to ensure correct operation.

The Post scaling concept is illustrated below for a Direct Form I biquad implementation.

Figure 4: Direct Form I structure with post scaling.

Pre-multiplying the numerator coefficients with the section gain, \(K\), each coefficient can now be scaled by \(G\), i.e. \(\displaystyle b_0=\frac{b_0}{G}, b_1=\frac{b_1}{G}, a_1=\frac{a_1}{G}, a_2=\frac{a_2}{G}\) and etc. This now results in the following difference equation:

\(\displaystyle y(n)=G \times\Big [b_0 x(n) + b_1 x(n-1) + b_2 x(n-2) – a_1 y(n-1)-a_2 y(n-2)\Big]\)

All IIR structures implemented within the tool include the Post Scaling Factor concept. This scaling is mandatory for implementation via the Arm CMSIS-DSP framework – see the configuration section for more details.

Understanding the filter summary

In order to fully understand the information presented in the ASN Filter Designer filter summary, the following example illustrates the filter coefficients obtained with Double Precision arithmetic and with Fixed Point Q15 quantisation.

Applying Fixed Point Q15 arithmetic (note the effects of quantisation on the coefficient values):

Configuring the ASN Filter Designer for Fixed Point arithmetic

In order to implement an IIR fixed point filter via the CMSIS-DSP framework, all designs must be based on Fixed Point arithmetic (either Q15 or Q31) and the Direct Form I filter structure.

Quantisation and filter structure settings can be found under the Q tab (as shown on the left): Setting Arithmetic to Fixed Point and Structure to Direct Form I and clicking on the Apply button configures the IIR considered herein for the CMSIS-DSP software framework.

The Post Scaling Factor is actually implemented in the CMSIS-DSP software framework as \( \log_2 G\) (i.e. a shift left scaling operation as depicted in Figure 4).

 

Built in analytics: the tool will automatically analyse the cascade’s filter coefficients and choose an appropriate scaling factor. As seen above, as the largest minimum value is -1.63143, thus, a Post Scaling Factor of 2 is required in order to ‘fit’ all of the coefficients into Q15 arithmetic.

Comparing spectra obtained by different arithmetic rules

In order to improve clarity and overall computation speed, the ASN Filter Designer only displays spectra (i.e. magnitude, phase etc.) based on the current arithmetic rules. This is somewhat different to other tools that display multi-spectra obtained by (for example) Fixed Point and Double Precision arithmetic. For any users wishing to compare spectra you may simply switch between arithmetic settings by changing the Arithmetic method. The designer will then automatically re-compute the filter coefficients using the selected arithmetic rules and the current technical specification. The chart will then be updated using the current zoom settings.

Automatic code generation to the Arm CMSIS-DSP framework

As with floating point arithmetic, select the Arm CMSIS-DSP framework from the selection box in the filter summary window:

The automatically generated C code based on the CMSIS-DSP framework for direct implementation on an Arm based Cortex-M processor is shown below:

As with the floating point filter, the automatic code generator generates all initialisation code, scaling and data structures needed to implement the IIR via the CMSIS-DSP library. This code may be directly used in any Cortex-M based development project – a complete Keil MDK example is available on Arm/Keil’s website. Notice that the tool’s code generator produces code for the Cortex-M4 core as default, please refer to the table below for the #define definition required for all supported cores.

ARM_MATH_CM0 Cortex-M0 core. ARM_MATH_CM4 Cortex-M4 core.
ARM_MATH_CM0PLUS Cortex-M0+ core. ARM_MATH_CM7 Cortex-M7 core.
ARM_MATH_CM3 Cortex-M3 core.
ARM_MATH_ARMV8MBL ARMv8M Baseline target (Cortex-M23 core).
ARM_MATH_ARMV8MML ARMv8M Mainline target (Cortex-M33 core).

The main test loop code (not shown) centres around the arm_biquad_cascade_df2T_f32() function, which performs the filtering operation on a block of input data.

Complex coefficient IIR filters are currently not supported.

Validating the design with the signal analyser

A design may be validated with the signal analyser, where both time and frequency domain plots are supported. A comprehensive signal generator is fully integrated into the signal analyser allowing designers to test their filters with a variety of input signals, such as sine waves, white noise or even external test data.

For Fixed Point implementations, the tool allows designers to specify the Overflow arithmetic rules as: Saturate or Wrap. Also, the Accumulator Word Length may be set between 16-40 bits allowing designers to quickly find the optimum settings to suit their application.

 

Extra resources

  1. Digital signal processing: principles, algorithms and applications, J.Proakis and D.Manoloakis
  2. Digital signal processing: a practical approach, E.Ifeachor and B.Jervis.
  3. Digital filters and signal processing, L.Jackson.
  4. Step by step video tutorial of designing an IIR and deploying it to Keil MDK uVision.
  5. Implementing Biquad IIR filters with the ASN Filter Designer and the Arm CMSIS-DSP software framework (ASN-AN025)
  6. Keil MDK uVision example IIR filter project

 

 

Download demo now

 

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Deploying legacy analog filters to Arm Cortex-M processor cores

In recent years, major microcontroller IC vendors such as: ST, NXP, TI, ADI, Atmel/Microchip, Cypress, Maxim to name but a few have based their modern 32-bit microcontrollers on Arm’s Cortex-M processor cores. This exciting trend means that algorithms traditionally undertaken in expensive DSPs (digital signal processors) can now be integrated into a powerful low-cost and power efficient microcontroller packed full of a rich assortment of connectivity and peripheral options.

For many IC vendors, the coupling of DSP functionality with the flexibility of a low power microcontroller, has allowed them to offer their customers a generation of so called 32-bit enhanced microcontrollers suitable for a variety of practical applications. More importantly, this marriage of technologies has also allowed designers working on price critical IoT applications to implement complex algorithmic concepts, while at the same time keeping the overall product cost low and still achieving excellent low power performance.

Upgrading legacy analog filters with the ASN Filter Designer

Analog filters have been around since the beginning of electronics, ranging from simple inductor-capacitor networks to more advanced active filters with op-amps. As such, there is a rich collection of tried and tested legacy filter designs for a broad range of sensor measurement applications.

ASN’s FilterScript symbolic math scripting language offers designers the ability to take an existing analog filter transfer function and transform it to digital with just a few lines of code. The ASN Filter Designer’s Arm automatic code generator analyses the designed digital filter and then automatically generates Arm CMSIS-DSP compliant C code suitable for direct implementation a Cortex-M based microcontroller.

Arm CMSIS-DSP software framework

The Arm CMSIS-DSP (Cortex Microcontroller Software Interface Standard)  software framework is a rich collection of over sixty DSP functions (including various mathematical functions, such as sine and cosine; IIR/FIR filtering functions, complex math functions, and data types) developed by Arm that have been optimised for their range of Cortex-M processor cores. The framework makes extensive use of highly optimised SIMD (single instruction, multiple data) instructions, that perform multiple identical operations in a single cycle instruction. The SIMD instructions (if supported by the core) coupled together with other optimisations allow engineers to produce highly optimised signal processing applications for Cortex-M based micro-controllers quickly and simply.

Mathematically modelling an analog circuit

Consider the active pre-emphasis filter shown below. The pre-emphasis filter has found particular use in audio work, since it is necessary to amplify the higher frequencies of the speech spectrum, whilst leaving the lower frequencies unaffected. The R and C values shown are only indented for the example, more practical values will depend on the application.A powerful method of reproducing the magnitude and phases characteristics of the analog filter in a digital implementation, is to mathematically model the circuit. This circuit may be analysed using Kirchhoff’s law, since the sum of currents into the op-amp’s inverting input must be equal to zero for negative feedback to work correctly – this results in a transfer function with a negative gain.

Therefore, using Ohm’s law (i.e., \(I=\frac{V}{R}\)),

\(
\displaystyle\frac{X(s)}{R_3}=-\frac{U(s)}{C_1||R_2 + R_1}
\)

After some algebraic manipulation, it can be seen that an expression for the circuit’s closed loop gain may be expressed as,

\(
\displaystyle\frac{X(s)}{U(s)}=-\frac{R_3}{R_1}\frac{\left(s+\frac{1}{R_2C_1}\right)}{\left(s+\frac{R_1+R_2}{R_1R_2C_1}\right)}
\)

substituting the values shown in the circuit diagram into the developed transfer function, yields

\(
\displaystyle H(s)=-10\left(\frac{s+1000}{s+11000}\right)
\)

What sampling rate do we need?

Analysing the cut-off frequencies in \(H(s)\), we see that the upper frequency is at \(11000 rad/sec\) or \(1.75kHz\). Therefore, setting the sampling rate to \(16kHz\) should be adequate for modelling the filter in the digital domain.

The sampling rate options are avaliabe in the main filter design UI  (shown on the left).

 

ASN FilterScript

\(H(s)\) can be easily specified in FilterScript with the analogtf function, as follows:

Nb={1,1000};
Na={1,11000};

Ha=analogtf(Nb,Na,-10,"symbolic");

Notice how the negative gain may also be entered directly into function’s argument. The symbolic keyword generates a symbolic transfer function representation in the command window.

Applying the Bilinear z-transformation via the bilinear command, i.e.

Hd=bilinear(Ha,"symbolic");


Notice how the bilinear command automatically scales numerator coefficients by -1, in order to account for the effect of the negative gain. The complete code is shown below:

Main()

Nb={1,1000};
Na={1,11000};

Ha=analogtf(Nb,Na,-10,"symbolic");
Hd=bilinear(Ha,"symbolic");

Num=getnum(Hd);
Den=getden(Hd);
Gain=getgain(Hd);

A comparison of the analog and discrete magnitude and phase spectra is shown below. Analysing the spectra, it can be seen that for a sampling rate of 16kHz the analog and digital filters are almost identical! This demonstrates the relative ease with which a designer can port their existing legacy analog designs into digital.

Automatic code generation to Arm Cortex-M processors

As mentioned at the beginning of this article, the ASN filter designer’s automatic code generation engine facilitates the export of a designed filter to Cortex-M Arm based processor cores via the CMSIS-DSP software framework. The tool’s built-in analytics and help functions assist the designer in successfully configuring the design for deployment.

All floating point IIR filters designs must be based on Single Precision arithmetic and either a Direct Form I or Direct Form II Transposed filter structure. The Direct Form II Transposed structure is advocated for floating point implementation by virtue of its higher numerically accuracy.

Quantisation and filter structure settings can be found under the Q tab (as shown on the left). Setting Arithmetic to Single Precision and Structure to Direct Form II Transposed and clicking on the Apply button configures the IIR considered herein for the CMSIS-DSP software framework.


The H2 filter (i.e. the filter designed in FilterScript) now needs to be re-optimised (transformed) to an H1 filter (main filter) structure for deployment. The options menu can be found under the P-Z tab in the main UI.

Arm CMSIS-DSP application C code

Select the Arm CMSIS-DSP framework from the selection box in the filter summary window:

The automatically generated C code based on the CMSIS-DSP framework for direct implementation on an Arm based Cortex-M processor is shown below:

As seen, the automatic code generator generates all initialisation code, scaling and data structures needed to implement the IIR via the CMSIS-DSP library. This code may be directly used in any Cortex-M based development project – a complete Keil MDK example is available on Arm/Keil’s website. Notice that the tool’s code generator produces code for the Cortex-M4 core as default, please refer to the table below for the #define definition required for all supported cores.

ARM_MATH_CM0 Cortex-M0 core. ARM_MATH_CM4 Cortex-M4 core.
ARM_MATH_CM0PLUS Cortex-M0+ core. ARM_MATH_CM7 Cortex-M7 core.
ARM_MATH_CM3 Cortex-M3 core.
ARM_MATH_ARMV8MBL ARMv8M Baseline target (Cortex-M23 core).
ARM_MATH_ARMV8MML ARMv8M Mainline target (Cortex-M33 core).

The main test loop code (not shown) centres around the arm_biquad_cascade_df2T_f32() function, which performs the filtering operation on a block of input data.

What have we learned?

The ASN Filter Designer provides engineers with everything they need in order to port legacy analog filter designs to a variety of Cortex-M processor cores.

The FilterScript symbolic math scripting language offers designers the ability to take an existing analog filter transfer function and transform it to digital (via the Bilinear z-transform or matched z-transform) with just a few lines of code.

The Arm automatic code generator analyses the designed digital filter and then automatically generates Arm CMSIS-DSP compliant C code suitable for direct implementation on a Cortex-M based microcontroller.

Extra resources

  1. Step by step video tutorial of designing an IIR and deploying it to Keil MDK uVision.
  2. Implementing Biquad IIR filters with the ASN Filter Designer and the Arm CMSIS-DSP software framework (ASN-AN025)
  3. Keil MDK uVision example IIR filter project

 

 

Download demo now

 

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How drones fuel ‘smart air’: The eye in the sky

Besides delivery, drones are already used as an ‘eye in the sky’. Or, with a ultrawide band radar attached to the drone, you can fly the drone wherever you want, maybe land the drone and start measuring. For instance:

  • It helps farmer to get higher yields by giving them a literal overview which spots on their field are developing well and which spots are perfoming less. So that farmers can take action on the lower performing spots.
  • Drones have excellent use for finding spots for roads, waterworks, energy fields and other infrastructure.
  • Drones give a real-time situation overview. As an example: an overview of road congestion to aid the city council to take proper action
  • They can measure while covering large areas. For instance: a large crop field where only the first crops from the road are visible for a farmer. Furthermore, they have the advantage that big areas can be captured in one glance
  • At places where humans have difficulty or is dangerous to reach. Think about places in the jungle or large mountainous regions. But also: an aid in building and maintenance of buildings and constructions like large building sites, bridges and high towers. Or when action on dangerous gasses is needed. And maybe, drones can become an aid to perform reparations and make installations themselves
  • For better and worse, drones can also be used for guarding assets. With sensors, they can guard areas by looking for movement, and establish a protected zone. Unfortunately, the technology is also available for terrorists, who will also find a use for drones for maximising chaos

Privacy, Safety and Security

Especially in crowded areas, privacy is a big issuse. A big complaint is the noise that drones produce: in a 2017 study, NASA found out that people find the noise of drones more annoying than the sound of ‘normal’ traffic. Besides noise, privacy has another factor: the camera. Besides that, drones may fly unasked over your property, what do they register exactly? What if you don’t want to be filmed in your garden?

Another practical problem is the risk that a drone can drop its cargo. Or that it can fall out of air itself. Amazon is already experimenting with a self-destroying drone when the drone risks crashing. In crowded areas, the risk of damage or even worse: hitting someone can’t be overlooked.

For acceptance of the use of drones, these challenges have to be resolved for getting trust and acceptance. Legislation is expected to come in to regulate drone traffic.

Security

As anyone can and will buy a drone, security is another issue. Anyone can just buy one online or even in a toystore and fly with it anywhere they want. The annoying noise of a drone in natural parks might be a inconvenience. But of course, more harmful use of drones might take place as well, for instance when used by terrorists, who can use drones for unwanted inspection and creating chaos. But also: you can load anything on your drone, fly to your destination and place it into action. Governments can forbid the flying of drones in the proximity of (for instance) a nuclear powerplant, but how do you prevent someone actually flying it there? Where a lot of questions of drone-flying have some potential answers, this one is still unsolved.

In all cases, sensors play a pivotal role in solving the technical questions. ASN Filter Designer can help with sensor measurement with real-time feedback and the powerful signal analyzer. How? Look at ASN Filter Designer or mail our consultancy service at: designs@advsolned.com

Do you agree with this list? Do you have other suggestions? Please let us know!