ASN Filter Designer’s new ANSI C SDK framework, provides developers with a comprehensive automatic C code generator for microcontrollers and embedded platforms. This allows developers to directly deploy their AIoT filtering application from within the tool to any STM32, Arduino, ESP32, PIC32, Beagle Bone and other Arm, RISC-V, MIPS microcontrollers for direct use.

Arm’s CMSIS-DSP library vs. ASN’s C SDK Framework

Thanks to our close collaboration with Arm’s architecture team, our new ultra-compact, highly optimised ANSI C based framework provides outstanding performance compared to other commercial DSP libraries, including Arm’s optimised CMSIS-DSP library.

Benchmarks for STM32: M3, M4F and M7F microcontrollers running an 8th order IIR biquad lowpass filter for 1024 samples

As seen, using o1 complier optimisation, our framework is able to surpass Arm’s CMSIS-DSP library’s performance on an M4F and M7F. Although notice that performance of both libraries is worse on the Cortex-M3, as it doesn’t have an FPU. Despite the difference, both libraries perform equally well, but the ASN DSP library has the added advantage of extra functionality and being platform agnostic, making it ideal for variety of biomedical (ECG, EMG, PPG), audio (sound effects, equalisers) , IoT (temperature, gas, pressure) and I4.0 (flow measurement, vibration analysis, CbM) applications.

AIoT applications designed on the newer Cortex-M33F and Cortex-M55F cores can also take advantage of extra filtering blocks, double precision arithmetic support, providing a simple way of implementing high performance AI on the Edge applications within hours.

Advantages for developers

  • A developer can now develop, test and deploy a complete DSP filtering application within the ASN Filter Designer within a few hours. This is very different from a traditional R&D approach that assigns a team of developers for several days in order to achieve the same level of accuracy required for the application.
  • Open source and agnostic code base: In order to allow developers to get the maximum performance for their applications, the ASN-DSP SDK is provided as open source and is written in ANSI C. This means that any embedded processor and any level of compiler optimisation can be used.
  • Memory size required for the ASN-DSP SDK is relativity lower than other standard DSP libraries, which makes the ASN-DSP SDK extremely suitable for microcontrollers that have memory constrains.
  • Using the ASN Filter Designer’s signal analyser tool, developers now can test the performance, accuracy and assess the frequency response of their designed filter and get optimised C code which they can directly use in their application.
  • The SDK also supports some extra filtering functions, such as: a median filter, a moving average filter, all-pass, single section IIR filters, a TKEO biomedical filter, and various non-linear functions, including RMS, Abs, Log and Sqrt.  These functions form the filter cascade within the tool, and can be used to build signal processing applications, such as EMG and ECG biomedical applications.
  • The ASN-DSP SDK supports both single and double precision floating point arithmetic, providing excellent numerical accuracy and wide dynamic range. The library is unique in the sense that it supports double precision arithmetic, which although is not the most optimal for microcontrollers, allows for the implementation of high-fidelity filtering applications.

The ANSI C SDK framework is further extended by our new C# .NET framework, allowing .NET developers to build high performance desktop applications with signal processing capabilities.

The both framework SDKs will be released with ASNFD v5.0 available for licensed users in September 2021.

Find out more

Benchmarks on a variety of 32-bit embedded platforms, including a biomedical EMG filtering example, are covered in the following application note.

Need more information or just want to be notified when release v5.0 is available? Please register your interest here.

Drones are one of the golden nuggets in AIoT. No wonder, they can play a pivotal role in congested cities and faraway areas for delivery. Further, they can be a great help to give an overview of a large area or for places which are difficult or dangerous to reach. Advanced Solutions did some research how the companies producing drones has solved some questions regarding their sensor technology. And in drones, there are a lot of sensors- and especial the DC motor control. We found out that with ASN Filter Designer, producers could have saved time and energy in the design of their algorithms with ASN Filter Designer.

Until now: hard-by found solutions

We found out that most producers had come very hard-by to their solutions. And that, when solutions are found, they are far from near perfect.

Probably, this producer has spent weeks or even months on finding these solutions. With ASN Filter Designer, he could have come to a solution within days or maybe hours. Besides, we expect that the measurement would be better too.

The most important issue is that algorithms were developed by handwork: developed in a ‘lab’ environment and then tried in real-life. With the result of the test, the algorithm would be adjusted again. Because a ‘lab’ environment where testing circumstances are stable, it’s very hard work to make the models work in ‘real’ life. For this, rounds and rounds of ‘lab development’ and ‘real life testing’ have to be made.

How ASN Filter Designer could have saved a lot of time and energy

ASN Filter Designer could have saved a lot of time in the design of the algorithms the following ways:

  • Design, analyze and implement filters for Drone senor applications 
  • Filters for speed and positioning control using sensorless BLDC motors
  • Speed up deployment

Real-time feedback and powerful signal analyzer

One of the key benefits of the ASN Filter Designer and signal analyzer is that it gives real-time feedback. Once an algorithm is developed, it can easily be tested on real-life data. To capture the real-life data, the ASN Filter Designer has a powerful signal analyzer in place. The tool’s signal analyzer implements a robust zero-crossings detector, allowing engineers to evaluate and fine-tune a complete sensorless BLDC control algorithm quickly and simply.

Design and analyze filters the easy way                         

You can easily design, analyze and implement filters for drone sensor applications. Including: loadcells, strain gauges, torque, pressure, temperature, vibration and ultrasonic sensors. And assess their dynamic performance in real-time with different input conditions.  With the ASN Filter Designer, no algorithms are needed: you just have to drag the filter design. The tool calculates the coordinates itself.

For speed and position control using sensorless BLDC (brushless DC) motors based on back-EMF filtering you can easily experiment with the ASN Filter Designer. See the results in real-time for various IIR, FIR and median (majority filtering) digital filtering schemes. The tool’s signal analyzer implements a robust zero-crossings detector. So you can evaluate and fine-tune a complete sensorless BLDC control algorithm quickly and simply.

Speed up deployment

Perform detailed time/frequency analysis on captured test datasets and fine-tune your design. Our Arm CMSIS-DSP and C/C++ code generators and software frameworks speed up deployment to a DSP, FPGA or micro-controller.

Drones use lots of sensors, and most challenges will be solved with them! ASN Filter Designer provides you with a simple way of improving your sensor measurement performance with its interactive design interface.

So, if you have a measurement problem, ask yourself: will I have a lot of frustrating and costs (maybe not ‘out of pocket’, but still: costs) of creating a filter by hand? Or would I create my filter within days or even hours and save a lot of headache and money. Because: it’s already possible to have a full 3-month license for only 140 euro!

An all-pass equalisation filter cascade (Heq) is available for equalising the phase response of the H1 filter cascade and H2 filter respectively.

Many Audio/acoustics engineers and researchers and audio hobbyists work with DSP (Digital Signal Processing). Some now and then, some on daily basis. Working on DSP for audio and speech, common challenges to create digital filters are: Noise cancellation, due to interference and Audio and Speech enhancement. And for whom DSP is not his daily job: filter design in general. In this blog, you’ll find out how the ASN Filter Designer may help for both experienced audio engineers and engineers where DSP is not their daily job to create digital filters for audio and speech.

For whom? For those with some and experienced DSP knowledge alike

If you are a audio/acoustics engineer or researcher or hobbyist: ASN Filter Designer is tailored for whom DSP is not his daily job and with some knowledge DSP. For those who need filter design and have to create some signal analysis. But also for those whom DSP is his daily job and want to save time and money. Most engineers who are working with DSP on a daily basis, are usually working with extensive but also expensive tools. Or want to do the maths themselves. Also for them ASN Filter Designer is useful:

  • Intuitive and easy to use
  • Save days of time spending calculating on your own for the price of 2-3 hours of work
  • Few lesser costs then extensive tooling with features you don’t use anyway
  • Automatic code generation: export for further analysis to MATLAB, etc, or to Cortex-M Arm based processors via the Arm CMSIS-DSP software framework

How DSP for Speech and audio benefit from ASN Filter Designer:

  • Experiment with a variety of equalisation, noise cancellation and sound effect audio filtering algorithms
  • Perform data analysis in the frequency domain and via specialised methods, including Cepstral analysis on the streaming data
  • Import your own wav audio files (mono or stereo up to 48kHz) for streaming, and modify the filter characteristics in real-time while listening to the filtered audio stream

Some features for creating digital filters for Audio and Speech:


The sampling frequency may be specified up to 4 decimal places

Sampling frequency

which is useful for designing filters based on fractional sampling frequencies, such as multiples of the 44.1kHz audio standard. Common examples include audio interpolation filters: 44.1kHz × 128 = 5.6448MHz and 44.1kHz × 256 = 11.2896MHz.

Filter orders of up to 499

may be constructed, where this is limited to 200 for streaming audio applications. As with the IIR filters, a FIR’s zeros may be modified by the P-Z editor (Method dropdown list changes to User defined), including the ability of adding poles and converting it into an IIR filter

Audio and user data playback streaming

Signal Generator Controller: 
Choose what you want to listen to; Adjust the amplitude of the input signal
Signal Generator Controller:
Choose what you want to listen to; Adjust the amplitude of the input signal

The signal analyzer allows designers to test their design on audio, real (user) data or synthetic data via the built-in signal generator. Default data playback is implemented as streaming data, providing a simple way of assessing the filter’s dynamic performance, which is especially useful for fixed point implementations. Both frequency domain and time domain charts are fully supported, allowing for design verification via transfer function estimation using the cross and power spectral density functions. As with all other charts, the signal analyzer chart fully supports advanced zooming and panning, as well as comprehensive chart data file export options.

Load .wav for playback

The signal generator allows you to load .wav audio files for playback via the Audio File method. Both mono and stereo formats are fully supported for 8.000, 11.025, 16.000, 22.05 and 44.1kHz. sampling rates. There is no restriction as to the length of the .wav file

You may add extra signals to input audio stream

20 extra signals for an IIR filter this is set at 20, 200 for an FIR

Intuitive data analysis with the mouse

Move the mouse over the chart will automatically produce data markers and data analytics (shown at the bottom right side of the GUI). The signal analyzer is directly coupled to the filter designer GUI. This means that you may modify the filter characteristics. And see the effects in real-time in the signal analyzer. This functionality is very useful when designing audio filters, as the new filter settings can be heard immediately on the streaming audio feed

Digital filters commonly used in audio and speech

speech and audio engineer researcher working on DSP digital filters microphone headphone

The ASN Filter designer includes digital filters commonly used in audio such as:

Read review here:

Top marks from Jacob Beningo

Joseph Yiu ARM Cortex ASN Filter Designer DSP portrait

New book on Arm’s latest processors:  The Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors. The book is written by Joseph Yiu, Arm’s resident architecture guru. It features benchmarks and experiments with our DSP filter design tooling (ASN Filter Designer) using CMSIS-DSP for Arm’s latest processors

We’re proud that Dr. Sanjeev Sarpal, Director of AI at Advanced Solutions Nederland has provided support in the digital filter design topic. We’re also very pleased to announce that Joseph Yiu’s new book features a chapter on the ASN Filter Designer for AI/IoT applications using the M23 and M33 Cortex-M cores. Advanced Solutions Nederland works closely with Arm’s DSP/architecture team for AI/DSP solutions using their cores. We’re currently working with Arm on releasing whitepapers on the Cortex-M55.

Armv8-M architecture and its features

The Definitive Guide to Arm® Cortex®-M23 and Cortex-M33 Processors focuses on the Armv8-M architecture and the features that are available in the Cortex-M23 and Cortex- M33 processors.

This book covers a range of topics, including:

  • the instruction set
  • the programmer’s model
  • interrupt handling
  • OS support
  • debug features

It demonstrates how to create software for the Cortex-M23 and Cortex-M33 processors by way of a range of examples. This enables embedded software developers to understand the Armv8-M architecture.

Worked out examples with ASN Filter Designer

Joseph Yiu’s new book features a chapter on the ASN Filter Designer for AI/IoT applications using the M23 and M33 Cortex-M cores. Our Director of AI, Dr. Sanjeev Sarpal, has provided support.

“The ASN Filter Designer Professional software supports a wide range of filter types. Its design allows filters to be designed via an interactive user interface, where various parameters can be adjusted and the design’s output can immediately be viewed. It also supports the simulation of the filter’s response so that the simulation outputs can be examined to determine whether the filter meets the requirements of the application. An added bonus, for developers creating software for Cortex-M processors, is that it generates C code that directly call CMSIS-DSP library functions (the designed filters can also be exported to C/C++, Python, Matlab, etc.).”

Joseph Yiu ASN Filter Designer Defining the frequency response of the filter
Defining the frequency response of the filter

“A number of commercial filter-design software tools are designed specifically for filter-design tasks and make it easier tot analyze a filters’ characteristics. For software developers who are not familiar with filter designs, these tools can be a great help” (p. 820). Thereby, Joseph Yiu uses the ASN Filter Designer for worked out examples. He creates a low pass biquad filter for a system with 48kHz sampling rate and with single-precision floating-point data type.

Definitive Guide Arm Cortex Joseph Yiu ASN Filter Designer

Order your copy here

What are Finite Impulse Respsonse (FIR) Filters? And how to design FIR Filters in ASN Filter Designer and which filters does ASN Filter Designer support?

The P-Z (pole-zero) editor, comprehensive and easy to use pole-zero editor. Together with useful options not commonly found in other filter design software.

DSP for engineers: the ASN Filter Designer is the ideal tool to analyze and filter the sensor data quickly. Create an algorithm within hours instead of days. When you are working with sensor data, you probably recognize these challenges:

  • My sensor data signals are too weak to even make an analysis. So, strengthening of the signals is needed
  • Where I would expect a flat line, the data looks like a mess because of interference and other containments. I need to clean the data first before analysis
Sensor data: wanted components, desired signals (DC components), and unwanted components (50HZ sine powerline interference, white noise). Filter sensor data DSP

Until now, you’ve probably spent days or even weeks working on your signal analysis and filtering? The development trajectory is generally slow and very painful.

In fact, just think about the number of hours that you could have saved if you had design tool that managed all of the algorithmic details for you. ASN Filter Designer is an industry standard solution used by thousands of professional developers worldwide working on IoT projects.

Our close collaboration with Arm and ST ensures that all designed filters are 100% compatible with all Arm Cortex-M processors, such as ST’s popular STM32 family.

Challenges for engineers

  • 90% of IoT smart sensors are based on Arm Cortex-M processor technology
  • Sensor signal processing is difficult
  • Sensors have trouble with all kinds of interference and undesirable components
  • How do I design a filter that meets my requirements?
  • How can I verify my designed filter on test data?
  • Clean sensor data is required for better product performance
  • Time consuming process to implement a filter on an embedded processor
  • Time is money!

Designers hit a ‘brick wall’ with traditional tooling. Standard tooling requires an iterative, trial and error approach or expert knowledge. Using this approach, a considerable amount of valuable engineering time is wasted. ASN Filter Designer helps you with an interactive method of design, whereby the tool automatically enters the technical specifications based on the graphical user requirements.

Fast DSP algorithm development

  • Fully validated filter design: suitable for deployment in DSP, micro-controller, FPGA, ASIC or PC application.
  • Automatic detailed design documentation: expediting peer review and lowing project risks by helping the designer create a paper trail.
  • Simple handover: project file, documentation and test results provide a painless route for handover to colleagues or other teams.
  • Easily accommodate other scenarios in the future: Design may be simply modified in the future to accommodate other requirements and scenarios, such as 60Hz powerline interference cancellation, instead of the European 50Hz.

ASN Filter Designer: the fast and intuitive filter designer

The ASN Filter Designer is the ideal tool to analyze and filter the sensor data quickly. When needed, you can easily deploy your data for further analyze for tools such as Matlab and Python. As such it’s ideal for engineers who need and powerful signal analyser and need to create a data filter for their IoT application. Certainly, when you have to create data filtering once in a while. Compared to other tools, you can create an algorithm within hours instead of days.

Easily deploy your algorithms to Matlab, Python, C++ and Arm

A big timesaver of the ASN Filter Designer is that you can easily deploy your algorithms to Matlab, Python, C++ or directly on an Arm microcontroller with the automatic code generators.

Instant pain relief

Just think about the number of hours that you could have saved if you had design tool that managed all of the algorithmic details for you.

ASN Filter Designer is an industry standard solution used by thousands of professional developers worldwide working on IoT projects. Our close collaboration with Arm and ST ensures that the all filters are 100% compatible with all Arm Cortex-M processors.

How much pain relief can 125 Euro buy you?

Because a lot of engineers need our ASN Filter Designer for a short time, a 125 Euro license for just 3 months is possible!

Just ask yourself: is 125 Euro a fair price to pay for instant pain relief and results? We think so. Besides, we have a license for 1 year and even a perpetual license. Download the demo to see for yourself or contact us for more information.

 

 

Download demo now

Licencing information

Finite impulse response (FIR) filters are useful for a variety of sensor signal processing applications, including audio and biomedical signal processing. Although several practical implementations for the FIR exist, the Direct Form Transposed structure offers the best numerical accuracy for floating point implementation. However, when considering fixed point implementation on a micro-controller, the Direct Form structure is considered to be the best choice by virtue of its large accumulator that accommodates any intermediate overflows.

This application note specifically addresses FIR filter design and implementation on a Cortex-M based microcontroller with the ASN Filter Designer for both floating point and fixed point applications via the Arm CMSIS-DSP software framework. Details are also given (including an Arm reference software pack) regarding implementation of the FIR filter in Arm/Keil’s MDK industry standard Cortex-M micro-controller development kit.

Introduction

ASN Filter Designer provides engineers with a powerful DSP experimentation platform, allowing for the design, experimentation and deployment of complex FIR digital filter designs for a variety of sensor measurement applications. The tool’s advanced functionality, includes a graphical based real-time filter designer, multiple filter blocks, various mathematical I/O blocks, live symbolic math scripting and real-time signal analysis (via a built-in signal analyser). These advantages coupled with automatic documentation and code generation functionality allow engineers to design and validate a digital filter within minutes rather than hours.

The Arm CMSIS-DSP (Cortex Microcontroller Software Interface Standard) software framework is a rich collection of over sixty DSP functions (including various mathematical functions, such as sine and cosine; IIR/FIR filtering functions, complex math functions, and data types) developed by Arm that have been optimised for their range of Cortex-M processor cores.

CMSIS compliant

The framework makes extensive use of highly optimised SIMD (single instruction, multiple data) instructions, that perform multiple identical operations in a single cycle instruction. The SIMD instructions (if supported by the core) coupled together with other optimisations allow engineers to produce highly optimised signal processing applications for Cortex-M based micro-controllers quickly and simply.

ASN Filter Designer fully supports the CMSIS-DSP software framework, by automatically producing optimised C code based on the framework’s DSP functions via its code generation engine.

Designing FIR filters with the ASN Filter Designer

ASN Filter Designer provides engineers with an easy to use, intuitive graphical design development platform for FIR digital filter design. The tool’s real-time design paradigm makes use of graphical design markers, allowing designers to simply draw and modify their magnitude frequency response requirements in real-time while allowing the tool automatically fill in the exact specifications for them.

Consider the design of the following technical specification:

Fs:500Hz
Passband frequency:0-25Hz
Type:Lowpass
Method:Parks-McClellan
Stopband attenuation @ 125Hz: ≥ 80 dB
Passband ripple:< 0.01dB
Order:Small as possible

Graphically entering the specifications into the ASN Filter Designer, and fine tuning the design marker positions, the tool automatically designs the filter), automatically choosing the required filter order, and in essence – automatically producing the filter’s exact technical specification!

The frequency response of a filter meeting the specification is shown below:

Low pass filter

This Lowpass filter will form the basis of the discussion presented herein.

Parks–McClellan algorithm

The Parks–McClellan algorithm is an iterative algorithm for finding the optimal Chebyshev FIR filter. The algorithm uses an indirect method for finding the optimal filter coefficients, that offers a degree of flexibility over other FIR design methods, in that each band may be individually customised in order to suit the designer’s requirements.

The primary FIR filter designer UI implements the Parks-McClellan algorithm, allowing for the design of the following filter types:

Filter TypesDescription
LowpassDesigns a lowpass filter.
HighpassDesigns a highpass filter.
BandpassDesigns a bandpass filter.
BandstopDesigns a bandstop filter.
MultibandDesigns a multiband filter with an arbitrary frequency response.
Hilbert transformerDesigns an all-pass filter with a -90 degree phase shift.
DifferentiatorDesigns a filter with +20dB/decade slope and +90 degree phase shift.
Double Differentiator Designs a filter with +40dB/decade slope and a +90 degree phase shift.
IntegratorDesigns a filter with -20dB/decade slope and a -90 degree phase shift.
Double IntegratorDesigns a filter with  -40dB/decade slope and a -90 degree phase shift.

These ten filter types provide designers with a great deal of flexibility for a variety of IoT applications. Design requirements may be simply specified via the use of the design markers. In all cases, the tool will automatically calculate the required filter order to meet the designer’s specification.

The Parks-McClellan algorithm is an optimal Chebyshev FIR design method. However, the algorithm may not converge for some specifications. In such cases, increasing the distance between the design marker bands generally helps.

Other FIR design methods

Designers looking to experiment with other types of FIR design methods may use the ASN FilterScript live symbolic math scripting language. The scripting language supports over 65 scientific commands and provides designers with a familiar and powerful programming language, while at the same time allowing them to implement complex symbolic mathematical expressions. The following functions are supported:

Function Description
movaverMoving average FIR filter design.
firwinFIR filter design based on the Window method.
firarbDesigns an FIR Window based filter with an arbitrary magnitude response.
firkaiserDesigns an FIR filter based on the Kaiser window method.
firgaussDesigns an FIR Gaussian lowpass filter.
savgolayDesign an FIR Savitzky-Golay lowpass smoothing filter.

Please refer to the ASN FilterScript reference guide for more details.

All filters designed in ASN FilterScript are designed using double precision arithmetic in the H2 filter sandbox. An H2 filter must be transformed to an H1 (primary) filter for deployment.

This may be simply achieved via the P-Z options menu:

re-optimise filter design

The re-optimise method automatically analyses and converts the H2 filter into an H1 filter.

Floating point implementation

When implementing a filter in floating point (i.e. using double or single precision arithmetic) the Direct Form Transposed structure is considered the most numerically accurate. This can be readily seen by analysing the difference equations below (used for implementation), as the undesirable effects of numerical swamping are minimised, since floating point addition is performed on numbers of similar magnitude.

\(\displaystyle \begin{eqnarray}y(n) & = &b_0x(n) &+& w_1(n-1) \\ w_1(n)&=&b_1x(n) &+& w_2(n-1) \\ w_2(n)&=&b_2x(n) &+& w_3(n-1) \\ \vdots\quad &=& \quad\vdots &+&\quad\vdots \\ w_q(n)&=&b_qx(n) \end{eqnarray}\)

Direct form transpose (for floating point implementions)
Direct form transpose (for floating point implementions)

\(\displaystyle \begin{eqnarray}y(n) & = &b_0x(n) &+& w_1(n-1) \\ w_1(n)&=&b_1x(n) &+& w_2(n-1) \\ w_2(n)&=&b_2x(n) &+& w_3(n-1) \\ \vdots\quad &=& \quad\vdots &+&\quad\vdots \\ w_q(n)&=&b_qx(n) \end{eqnarray}\)

The quantisation and filter structure settings used to implement the FIR can be found under the Q tab (as shown below).

Despite the Direct Form Transposed structure being the most efficient for floating point implementation, the Arm CMSIS-DSP library does not currently support the Direct Form Transposed structure for FIR filters. Only the Direct Form structure is supported.

Setting Arithmetic to Single Precision and Structure to Direct Form and clicking on the Apply button configures the FIR considered herein for the CMSIS-DSP software framework.

The optimised functions within the Arm CMSIS-DSP framework currently support Single Precision arithmetic only.

Support for Double Precision and the Direct Form Transposed structure will be added in future releases.

Fixed point implementation

When implementing a filter with fixed point arithmetic, the Direct Form structure is considered to be the best choice by virtue of its large accumulator that accommodates any intermediate overflows. The Direct Form structure and associated difference equation are shown below.

\(\displaystyle y(n) = b_0x(n) + b_1x(n-1) + b_2x(n-2) + …. +b_qx(n-q) \)

Direct form structure (for fixed point implementation), Direct form fixed point
Direct form structure (for fixed point implementation)

The CMSIS-DSP Framework supports Q7, Q15 and Q31 coefficient quantisation only. The options may be simply specified via the quantisation tab Q as shown below:

ASN Filter Designer direct form

The tool’s inbuilt analytics (shown in the textbox) are intended to help the designer choose the most suitable quantisation settings.

As seen on the left, the tool has recommended a RFWL (recommended fraction length) of 15bits (Q15) for the coefficients, which is as required.

The Direct form structure is chosen over the Direct Form Transposed as a single (40-bit) accumulator can be used. The tool’s automatic code generator makes use of CMSIS-DSP’s 64-bit accumulators functions, so that the final C code deployed to a Cortex-M device will not overflow.

Deploying Arm CMSIS-DSP compliant code

The ASN Filter Designer’s automatic code generation engine facilitates the export of a designed filter to Cortex-M Arm based processors via the Arm CMSIS-DSP software framework. The tool’s built-in analytics and help functions assist the designer in successfully configuring the design for deployment.

Select the Arm CMSIS-DSP framework from the selection box in the filter summary window:

Arm-CMSIS implementation

The automatically generated C code based on the Arm CMSIS-DSP framework for direct implementation on an Arm based Cortex-M processor is shown below:

C code Arm CMSIS DSP for direct implementation on an Arm based Cortex-M processor

This code may be directly used in any Cortex-M based development project.

Arm Keil’s MDK (uVision)

As mentioned above, the code generated by the Arm CMSIS DSP code generator may be directly used in any Cortex-M based development project tooling, such as Arm Keil’s industry standard uVision MDK (micro-controller development kit).

The following Arm software pack is available on Keil’s website for using this code directly with Keil uVision MDK.

Arm Keil MDK Filter Design

 

 

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Licencing information

Although the design of FIR filters with linear phase is an easy task. This is certainly not true for IIR filters that usually have a highly non-linear phase response, especially around the filter’s cut-off frequencies. This article discusses the characteristics needed for a digital filter to have linear phase, and how an IIR filter’s passband phase can be modified in order to achieve linear phase using all-pass equalisation filters.

Why do we need linear phase filters?

Digital filters with linear phase have the advantage of delaying all frequency components by the same amount, i.e. they preserve the input signal’s phase relationships. This preservation of phase means that the filtered signal retains the shape of the original input signal. This characteristic is essential for audio applications as the signal shape is paramount for maintaining high fidelity in the filtered audio. Yet another application area that requires this, is ECG biomedical waveform analysis, as any artefacts introduced by the filter may be misinterpreted as heart anomalies.

The following plot shows the filtering performance of a Chebyshev type I lowpass IIR on ECG data – input waveform (shown in blue) shifted by 10 samples (\(\small \Delta=10\)) to approximately compensate for the filter’s group delay. Notice that the filtered signal (shown in red) has attenuated, broadened and added oscillations around the ECG peak, which is undesirable.

Figure 1: IIR lowpass filtering result with phase distortion

In order for a digital filter to have linear phase, its impulse response must have conjugate-even or conjugate-odd symmetry about its midpoint. This is readily seen for an FIR filter,

\(\displaystyle H(z)=\sum\limits_{k=0}^{L-1} b_k z^{-k}\tag{1} \)

With the following constraint on its coefficients,

\(\displaystyle b_k=\pm\, b^{\ast}_{L-1-k}\tag{2} \)

which leads to,

\(\displaystyle z^{L-1}H(z) = \pm\, H^\ast (1/z^\ast)\tag{3} \)

Analysing Eqn. 3, we see that roots (zeros) of \(\small H(z)\) must also be the zeros of  \(\small H^\ast (1/z^\ast)\). This means that the roots of \(\small H(z)\) must occur in conjugate reciprocal pairs, i.e.  if \(\small z_k\) is a zero of \(\small H(z)\), then \(\small H^\ast (1/z^\ast)\) must also be a zero.

Why IIR filters do not have linear phase

A digital filter is said to be bounded input, bounded output stable, or BIBO stable, if every bounded input gives rise to a bounded output. All IIR filters have either poles or both poles and zeros, and must be BIBO stable, i.e.

\(\displaystyle \sum_{k=0}^{\infty}\left|h(k)\right|<\infty \tag{4}\)

Where, \(\small h(k)\) is the filter’s impulse response. Analyzing Eqn. 4, it should be clear that the BIBO stability criterion will only be satisfied if the system’s poles lie inside the unit circle, since the system’s ROC (region of convergence) must include the unit circle. Consequently, it is sufficient to say that a bounded input signal will always produce a bounded output signal if all the poles lie inside the unit circle.

The zeros on the other hand, are not constrained by this requirement, and as a consequence may lie anywhere on z-plane, since they do not directly affect system stability. Therefore, a system stability analysis may be undertaken by firstly calculating the roots of the transfer function (i.e., roots of the numerator and denominator polynomials) and then plotting the corresponding poles and zeros upon the z-plane.

Applying the developed logic to the poles of an IIR filter, we now arrive at a very important conclusion on why IIR filters cannot have linear phase.

A BIBO stable filter must have its poles within the unit circle, and as such in order to get linear phase, an IIR would need conjugate reciprocal poles outside of the unit circle, making it BIBO unstable.

Based upon this statement, it would seem that it’s not possible to design an IIR to have linear phase. However, a discussed below, phase equalisation filters can be used to linearise the passband phase response.

Phase linearisation with all-pass filters

All-pass phase linearisation filters (equalisers) are a well-established method of altering a filter’s phase response while not affecting its magnitude response. A second order (Biquad) all-pass filter is defined as:

\( A(z)=\Large\frac{r^2-2rcos \left( \frac{2\pi f_c}{fs}\right) z^{-1}+z^{-2}}{1-2rcos \left( \frac{2\pi f_c}{fs}\right)z^{-1}+r^2 z^{-2}}\tag{5} \)

Where, \(\small f_c\) is the centre frequency, \(\small r\) is radius of the poles and \(\small f_s\) is the sampling frequency. Notice how the numerator and denominator coefficients are arranged as a mirror image pair of one another.  The mirror image property is what gives the all-pass filter its desirable property, namely allowing the designer to alter the phase response while keeping the magnitude response constant or flat over the complete frequency spectrum.

Cascading an APF (all-pass filter) equalisation cascade (comprised of multiple APFs) with an IIR filter, the basic idea is that we only need to linearise the phase response the passband region. The other regions, such as the transition band and stopband may be ignored, as any non-linearities in these regions are of little interest to the overall filtering result.

The challenge

The APF cascade sounds like an ideal compromise for this challenge, but in truth a significant amount of time and very careful fine-tuning of the APF positions is required in order to achieve an acceptable result. Each APF has two variables: \(\small f_c\) and \(\small r\) that need to be optimised, which complicates the solution. This is further complicated by the fact that the more APF stages that are added to the cascade, the higher the overall filter’s group delay (latency) becomes. This latter issue may become problematic for fast real-time closed loop control systems that rely on an IIR’s low latency property.

Nevertheless, despite these challenges, the APF equaliser is a good compromise for linearising an IIRs passband phase characteristics.

The APF equaliser

ASN Filter Designer provides designers with a very simple to use graphical all-phase equaliser interface for linearising the passband phase of IIR filters. As seen below, the interface is very intuitive, and allows designers to quickly place and fine-tune APF filters positions with the mouse. The tool automatically calculates \(\small f_c\) and \(\small r\), based on the marker position.

APF equaliser ASN Filter Designer

Right clicking on the frequency response chart or on an existing all-pass design marker displays an options menu, as shown on the left.

You may add up to 10 biquads (professional version only).

An IIR with linear passband phase

Designing an equaliser composed of three APF pairs, and cascading it with the Chebyshev filter of Figure 1, we obtain a filter waveform that has a much a sharper peak with less attenuation and oscillation than the original IIR – see below. However, this improvement comes at the expense of three extra Biquad filters (the APF cascade) and an increased group delay, which has now risen to 24 samples compared with the original 10 samples.

IIR lowpass filtering result with three APF phase equalisation filters
(minimal phase distortion)
IIR lowpass filtering result with three APF phase equalisation filters
(minimal phase distortion)

The frequency response of both the original IIR and the equalised IIR are shown below, where the group delay (shown in purple) is the average delay of the filter and is a simpler way of assessing linearity.

IIR without equalisation cascade
IIR without equalisation cascade

IIR with equalisation cascade
IIR with equalisation cascade

Notice that the group delay of the equalised IIR passband (shown on the right) is almost flat, confirming that the phase is indeed linear.

Automatic code generation to Arm processor cores via CMSIS-DSP

The ASN Filter Designer’s automatic code generation engine facilitates the export of a designed filter to Cortex-M Arm based processors via the CMSIS-DSP software framework. The tool’s built-in analytics and help functions assist the designer in successfully configuring the design for deployment.

Before generating the code, the IIR and equalisation filters (i.e. H1 and Heq filters) need to be firstly re-optimised (merged) to an H1 filter (main filter) structure for deployment. The options menu can be found under the P-Z tab in the main UI.

All floating point IIR filters designs must be based on Single Precision arithmetic and either a Direct Form I or Direct Form II Transposed filter structure. The Direct Form II Transposed structure is advocated for floating point implementation by virtue of its higher numerically accuracy.

Quantisation and filter structure settings can be found under the Q tab (as shown on the left). Setting Arithmetic to Single Precision and Structure to Direct Form II Transposed and clicking on the Apply button configures the IIR considered herein for the CMSIS-DSP software framework.

Select the Arm CMSIS-DSP framework from the selection box in the filter summary window:

The automatically generated C code based on the CMSIS-DSP framework for direct implementation on an Arm based Cortex-M processor is shown below:

The ASN Filter Designer's automatic code generator generates all initialisation code, scaling and data structures needed to implement the linearised filter IIR filter via Arm's CMSIS-DSP library.

The ASN Filter Designer’s automatic code generator generates all initialisation code, scaling and data structures needed to implement the linearised filter IIR filter via Arm’s CMSIS-DSP library.

What we have learnt

The roots of a linear phase digital filter must occur in conjugate reciprocal pairs. Although this no problem for an FIR filter, it becomes infeasible for an IIR filter, as poles would need to be both inside and outside of the unit circle, making the filter BIBO unstable.

The passband phase response of an IIR filter may be linearised by using an APF equalisation cascade. The ASN Filter Designer provides designers with everything they need via a very simple to use, graphical all-pass phase equaliser interface, in order to design a suitable APF cascade by just using the mouse!

The linearised IIR filter may be exported via the automatic code generator using Arm’s optimised CMSIS-DSP library functions for deployment on any Cortex-M microcontroller.

 

 

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