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Finite impulse response (FIR) filters are useful for a variety of sensor signal processing applications, including audio and biomedical signal processing. Although several practical implementations for the FIR exist, the Direct Form Transposed structure offers the best numerical accuracy for floating point implementation. However, when considering fixed point implementation on a micro-controller, the Direct Form structure is considered to be the best choice by virtue of its large accumulator that accommodates any intermediate overflows.

This application note specifically addresses FIR filter design and implementation on a Cortex-M based microcontroller with the ASN Filter Designer for both floating point and fixed point applications via the Arm CMSIS-DSP software framework. Details are also given (including an Arm reference software pack) regarding implementation of the FIR filter in Arm/Keil’s MDK industry standard Cortex-M micro-controller development kit.

Introduction

ASN Filter Designer provides engineers with a powerful DSP experimentation platform, allowing for the design, experimentation and deployment of complex FIR digital filter designs for a variety of sensor measurement applications. The tool’s advanced functionality, includes a graphical based real-time filter designer, multiple filter blocks, various mathematical I/O blocks, live symbolic math scripting and real-time signal analysis (via a built-in signal analyser). These advantages coupled with automatic documentation and code generation functionality allow engineers to design and validate a digital filter within minutes rather than hours.

The Arm CMSIS-DSP (Cortex Microcontroller Software Interface Standard) software framework is a rich collection of over sixty DSP functions (including various mathematical functions, such as sine and cosine; IIR/FIR filtering functions, complex math functions, and data types) developed by Arm that have been optimised for their range of Cortex-M processor cores.

The framework makes extensive use of highly optimised SIMD (single instruction, multiple data) instructions, that perform multiple identical operations in a single cycle instruction. The SIMD instructions (if supported by the core) coupled together with other optimisations allow engineers to produce highly optimised signal processing applications for Cortex-M based micro-controllers quickly and simply.

ASN Filter Designer fully supports the CMSIS-DSP software framework, by automatically producing optimised C code based on the framework’s DSP functions via its code generation engine.

Designing FIR filters with the ASN Filter Designer

ASN Filter Designer provides engineers with an easy to use, intuitive graphical design development platform for FIR digital filter design. The tool’s real-time design paradigm makes use of graphical design markers, allowing designers to simply draw and modify their magnitude frequency response requirements in real-time while allowing the tool automatically fill in the exact specifications for them.

Consider the design of the following technical specification:

Fs:500Hz
Passband frequency:0-25Hz
Type:Lowpass
Method:Parks-McClellan
Stopband attenuation @ 125Hz: ≥ 80 dB
Passband ripple:< 0.01dB
Order:Small as possible

Graphically entering the specifications into the ASN Filter Designer, and fine tuning the design marker positions, the tool automatically designs the filter), automatically choosing the required filter order, and in essence – automatically producing the filter’s exact technical specification!

The frequency response of a filter meeting the specification is shown below:

This Lowpass filter will form the basis of the discussion presented herein.

Parks–McClellan algorithm

The Parks–McClellan algorithm is an iterative algorithm for finding the optimal Chebyshev FIR filter. The algorithm uses an indirect method for finding the optimal filter coefficients, that offers a degree of flexibility over other FIR design methods, in that each band may be individually customised in order to suit the designer’s requirements.

The primary FIR filter designer UI implements the Parks-McClellan algorithm, allowing for the design of the following filter types:

Filter TypesDescription
LowpassDesigns a lowpass filter.
HighpassDesigns a highpass filter.
BandpassDesigns a bandpass filter.
BandstopDesigns a bandstop filter.
MultibandDesigns a multiband filter with an arbitrary frequency response.
Hilbert transformerDesigns an all-pass filter with a -90 degree phase shift.
DifferentiatorDesigns a filter with +20dB/decade slope and +90 degree phase shift.
Double Differentiator Designs a filter with +40dB/decade slope and a +90 degree phase shift.
IntegratorDesigns a filter with -20dB/decade slope and a -90 degree phase shift.
Double IntegratorDesigns a filter with  -40dB/decade slope and a -90 degree phase shift.

These ten filter types provide designers with a great deal of flexibility for a variety of IoT applications. Design requirements may be simply specified via the use of the design markers. In all cases, the tool will automatically calculate the required filter order to meet the designer’s specification.

The Parks-McClellan algorithm is an optimal Chebyshev FIR design method. However, the algorithm may not converge for some specifications. In such cases, increasing the distance between the design marker bands generally helps.

Other FIR design methods

Designers looking to experiment with other types of FIR design methods may use the ASN FilterScript live symbolic math scripting language. The scripting language supports over 65 scientific commands and provides designers with a familiar and powerful programming language, while at the same time allowing them to implement complex symbolic mathematical expressions. The following functions are supported:

Function Description
movaverMoving average FIR filter design.
firwinFIR filter design based on the Window method.
firarbDesigns an FIR Window based filter with an arbitrary magnitude response.
firkaiserDesigns an FIR filter based on the Kaiser window method.
firgaussDesigns an FIR Gaussian lowpass filter.
savgolayDesign an FIR Savitzky-Golay lowpass smoothing filter.

Please refer to the ASN FilterScript reference guide for more details.

All filters designed in ASN FilterScript are designed using double precision arithmetic in the H2 filter sandbox. An H2 filter must be transformed to an H1 (primary) filter for deployment.

This may be simply achieved via the P-Z options menu:

The re-optimise method automatically analyses and converts the H2 filter into an H1 filter.

Floating point implementation

When implementing a filter in floating point (i.e. using double or single precision arithmetic) the Direct Form Transposed structure is considered the most numerically accurate. This can be readily seen by analysing the difference equations below (used for implementation), as the undesirable effects of numerical swamping are minimised, since floating point addition is performed on numbers of similar magnitude.

\(\displaystyle \begin{eqnarray}y(n) & = &b_0x(n) &+& w_1(n-1) \\ w_1(n)&=&b_1x(n) &+& w_2(n-1) \\ w_2(n)&=&b_2x(n) &+& w_3(n-1) \\ \vdots\quad &=& \quad\vdots &+&\quad\vdots \\ w_q(n)&=&b_qx(n) \end{eqnarray}\)

Direct form transpose (for floating point implementions)

\(\displaystyle \begin{eqnarray}y(n) & = &b_0x(n) &+& w_1(n-1) \\ w_1(n)&=&b_1x(n) &+& w_2(n-1) \\ w_2(n)&=&b_2x(n) &+& w_3(n-1) \\ \vdots\quad &=& \quad\vdots &+&\quad\vdots \\ w_q(n)&=&b_qx(n) \end{eqnarray}\)

The quantisation and filter structure settings used to implement the FIR can be found under the Q tab (as shown below). Setting Arithmetic to Single Precision and Structure to Direct Form Transposed and clicking on the Apply button configures the FIR considered herein for the CMSIS-DSP software framework.

The optimised functions within the Arm CMSIS-DSP framework currently support Single Precision arithmetic only.

Support for Double Precision will be added in future releases.

Fixed point implementation

When implementing a filter with fixed point arithmetic, the Direct Form structure is considered to be the best choice by virtue of its large accumulator that accommodates any intermediate overflows. The Direct Form structure and associated difference equation are shown below.

\(\displaystyle y(n) = b_0x(n) + b_1x(n-1) + b_2x(n-2) + …. +b_qx(n-q) \)

Direct form structure (for fixed point implementation)

The CMSIS-DSP Framework supports Q7, Q15 and Q31 coefficient quantisation only. The options may be simply specified via the quantisation tab Q as shown below:

The tool’s inbuilt analytics (shown in the textbox) are intended to help the designer choose the most suitable quantisation settings.

As seen on the left, the tool has recommended a RFWL (recommended fraction length) of 15bits (Q15) for the coefficients, which is as required.

The Direct form structure is chosen over the Direct Form Transposed as a single (40-bit) accumulator can be used. The tool’s automatic code generator makes use of CMSIS-DSP’s 64-bit accumulators functions, so that the final C code deployed to a Cortex-M device will not overflow.

Deploying Arm CMSIS-DSP compliant code

The ASN Filter Designer’s automatic code generation engine facilitates the export of a designed filter to Cortex-M Arm based processors via the Arm CMSIS-DSP software framework. The tool’s built-in analytics and help functions assist the designer in successfully configuring the design for deployment.

Select the Arm CMSIS-DSP framework from the selection box in the filter summary window:

The automatically generated C code based on the Arm CMSIS-DSP framework for direct implementation on an Arm based Cortex-M processor is shown below:

This code may be directly used in any Cortex-M based development project.

Arm Keil’s MDK (uVision)

As mentioned above, the code generated by the Arm CMSIS DSP code generator may be directly used in any Cortex-M based development project tooling, such as Arm Keil’s industry standard uVision MDK (micro-controller development kit).

The following Arm software pack is available on Keil’s website for using this code directly with Keil uVision MDK.

 

 

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Although the design of FIR filters with linear phase is an easy task. This is certainly not true for IIR filters that usually have a highly non-linear phase response, especially around the filter’s cut-off frequencies. This article discusses the characteristics needed for a digital filter to have linear phase, and how an IIR filter’s passband phase can be modified in order to achieve linear phase using all-pass equalisation filters.

Why do we need linear phase filters?

Digital filters with linear phase have the advantage of delaying all frequency components by the same amount, i.e. they preserve the input signal’s phase relationships. This preservation of phase means that the filtered signal retains the shape of the original input signal. This characteristic is essential for audio applications as the signal shape is paramount for maintaining high fidelity in the filtered audio. Yet another application area that requires this, is ECG biomedical waveform analysis, as any artefacts introduced by the filter may be misinterpreted as heart anomalies.

The following plot shows the filtering performance of a Chebyshev type I lowpass IIR on ECG data – input waveform (shown in blue) shifted by 10 samples (\(\small \Delta=10\)) to approximately compensate for the filter’s group delay. Notice that the filtered signal (shown in red) has attenuated, broadened and added oscillations around the ECG peak, which is undesirable.

Figure 1: IIR lowpass filtering result with phase distortion

In order for a digital filter to have linear phase, its impulse response must have conjugate-even or conjugate-odd symmetry about its midpoint. This is readily seen for an FIR filter,

\(\displaystyle H(z)=\sum\limits_{k=0}^{L-1} b_k z^{-k}\tag{1} \)

With the following constraint on its coefficients,

\(\displaystyle b_k=\pm\, b^{\ast}_{L-1-k}\tag{2} \)

which leads to,

\(\displaystyle z^{L-1}H(z) = \pm\, H^\ast (1/z^\ast)\tag{3} \)

Analysing Eqn. 3, we see that roots (zeros) of \(\small H(z)\) must also be the zeros of  \(\small H^\ast (1/z^\ast)\). This means that the roots of \(\small H(z)\) must occur in conjugate reciprocal pairs, i.e.  if \(\small z_k\) is a zero of \(\small H(z)\), then \(\small H^\ast (1/z^\ast)\) must also be a zero.

Why IIR filters do not have linear phase

A digital filter is said to be bounded input, bounded output stable, or BIBO stable, if every bounded input gives rise to a bounded output. All IIR filters have either poles or both poles and zeros, and must be BIBO stable, i.e.

\(\displaystyle \sum_{k=0}^{\infty}\left|h(k)\right|<\infty \tag{4}\)

Where, \(\small h(k)\) is the filter’s impulse response. Analyzing Eqn. 4, it should be clear that the BIBO stability criterion will only be satisfied if the system’s poles lie inside the unit circle, since the system’s ROC (region of convergence) must include the unit circle. Consequently, it is sufficient to say that a bounded input signal will always produce a bounded output signal if all the poles lie inside the unit circle.

The zeros on the other hand, are not constrained by this requirement, and as a consequence may lie anywhere on z-plane, since they do not directly affect system stability. Therefore, a system stability analysis may be undertaken by firstly calculating the roots of the transfer function (i.e., roots of the numerator and denominator polynomials) and then plotting the corresponding poles and zeros upon the z-plane.

Applying the developed logic to the poles of an IIR filter, we now arrive at a very important conclusion on why IIR filters cannot have linear phase.

A BIBO stable filter must have its poles within the unit circle, and as such in order to get linear phase, an IIR would need conjugate reciprocal poles outside of the unit circle, making it BIBO unstable.

Based upon this statement, it would seem that it’s not possible to design an IIR to have linear phase. However, a discussed below, phase equalisation filters can be used to linearise the passband phase response.

Phase linearisation with all-pass filters

All-pass phase linearisation filters (equalisers) are a well-established method of altering a filter’s phase response while not affecting its magnitude response. A second order (Biquad) all-pass filter is defined as:

\( A(z)=\Large\frac{r^2-2rcos \left( \frac{2\pi f_c}{fs}\right) z^{-1}+z^{-2}}{1-2rcos \left( \frac{2\pi f_c}{fs}\right)z^{-1}+r^2 z^{-2}}\tag{5} \)

Where, \(\small f_c\) is the centre frequency, \(\small r\) is radius of the poles and \(\small f_s\) is the sampling frequency. Notice how the numerator and denominator coefficients are arranged as a mirror image pair of one another.  The mirror image property is what gives the all-pass filter its desirable property, namely allowing the designer to alter the phase response while keeping the magnitude response constant or flat over the complete frequency spectrum.

Cascading an APF (all-pass filter) equalisation cascade (comprised of multiple APFs) with an IIR filter, the basic idea is that we only need to linearise the phase response the passband region. The other regions, such as the transition band and stopband may be ignored, as any non-linearities in these regions are of little interest to the overall filtering result.

The challenge

The APF cascade sounds like an ideal compromise for this challenge, but in truth a significant amount of time and very careful fine-tuning of the APF positions is required in order to achieve an acceptable result. Each APF has two variables: \(\small f_c\) and \(\small r\) that need to be optimised, which complicates the solution. This is further complicated by the fact that the more APF stages that are added to the cascade, the higher the overall filter’s group delay (latency) becomes. This latter issue may become problematic for fast real-time closed loop control systems that rely on an IIR’s low latency property.

Nevertheless, despite these challenges, the APF equaliser is a good compromise for linearising an IIRs passband phase characteristics.

The APF equaliser

ASN Filter Designer provides designers with a very simple to use graphical all-phase equaliser interface for linearising the passband phase of IIR filters. As seen below, the interface is very intuitive, and allows designers to quickly place and fine-tune APF filters positions with the mouse. The tool automatically calculates \(\small f_c\) and \(\small r\), based on the marker position.

Right clicking on the frequency response chart or on an existing all-pass design marker displays an options menu, as shown on the left.

You may add up to 10 biquads (professional version only).

An IIR with linear passband phase

Designing an equaliser composed of three APF pairs, and cascading it with the Chebyshev filter of Figure 1, we obtain a filter waveform that has a much a sharper peak with less attenuation and oscillation than the original IIR – see below. However, this improvement comes at the expense of three extra Biquad filters (the APF cascade) and an increased group delay, which has now risen to 24 samples compared with the original 10 samples.

IIR lowpass filtering result with three APF phase equalisation filters
(minimal phase distortion)

The frequency response of both the original IIR and the equalised IIR are shown below, where the group delay (shown in purple) is the average delay of the filter and is a simpler way of assessing linearity.

IIR without equalisation cascade

IIR with equalisation cascade

Notice that the group delay of the equalised IIR passband (shown on the right) is almost flat, confirming that the phase is indeed linear.

Automatic code generation to Arm processor cores via CMSIS-DSP

The ASN Filter Designer’s automatic code generation engine facilitates the export of a designed filter to Cortex-M Arm based processors via the CMSIS-DSP software framework. The tool’s built-in analytics and help functions assist the designer in successfully configuring the design for deployment.

Before generating the code, the IIR and equalisation filters (i.e. H1 and Heq filters) need to be firstly re-optimised (merged) to an H1 filter (main filter) structure for deployment. The options menu can be found under the P-Z tab in the main UI.

All floating point IIR filters designs must be based on Single Precision arithmetic and either a Direct Form I or Direct Form II Transposed filter structure. The Direct Form II Transposed structure is advocated for floating point implementation by virtue of its higher numerically accuracy.

Quantisation and filter structure settings can be found under the Q tab (as shown on the left). Setting Arithmetic to Single Precision and Structure to Direct Form II Transposed and clicking on the Apply button configures the IIR considered herein for the CMSIS-DSP software framework.

Select the Arm CMSIS-DSP framework from the selection box in the filter summary window:

The automatically generated C code based on the CMSIS-DSP framework for direct implementation on an Arm based Cortex-M processor is shown below:

The ASN Filter Designer’s automatic code generator generates all initialisation code, scaling and data structures needed to implement the linearised filter IIR filter via Arm’s CMSIS-DSP library.

What we have learnt

The roots of a linear phase digital filter must occur in conjugate reciprocal pairs. Although this no problem for an FIR filter, it becomes infeasible for an IIR filter, as poles would need to be both inside and outside of the unit circle, making the filter BIBO unstable.

The passband phase response of an IIR filter may be linearised by using an APF equalisation cascade. The ASN Filter Designer provides designers with everything they need via a very simple to use, graphical all-pass phase equaliser interface, in order to design a suitable APF cascade by just using the mouse!

The linearised IIR filter may be exported via the automatic code generator using Arm’s optimised CMSIS-DSP library functions for deployment on any Cortex-M microcontroller.

 

 

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As discussed in a previous article, the moving average (MA) filter is perhaps one of the most widely used digital filters due to its conceptual simplicity and ease of implementation. The realisation diagram shown below, illustrates that an MA filter can be implemented as a simple FIR filter, just requiring additions and a delay line.

Modelling the above, we see that a moving average filter of length \(\small\textstyle L\) for an input signal \(\small\textstyle x(n)\) may be defined as follows:

\( y(n)=\large{\frac{1}{L}}\normalsize{\sum\limits_{k=0}^{L-1}x(n-k)}\quad \text{for} \quad\normalsize{n=0,1,2,3….}\label{FIRdef}\tag{1}\)

This computation requires \(\small\textstyle L-1\) additions, which may become computationally demanding for very low power processors when \(\small\textstyle L\) is large. Therefore, applying some lateral thinking to the computational challenge, we see that a much more computationally efficient filter can be used in order to achieve the same result, namely:

\(H(z)=\displaystyle\frac{1}{L}\frac{1-z^{-L}}{1-z^{-1}}\tag{2}\label{TF}\)

with the difference equation,

\(y(n) =y(n-1)+\displaystyle\frac{x(n)-x(n-L)}{L}\tag{3}\)

Notice that this implementation only requires one addition and one subtraction for any value of \(\small\textstyle L\). A further simplification (valid for both implementations) can be achieved in a pre-processing step prior to implementing the difference equation, i.e. scaling all input values by \(\small\textstyle L\). If \(\small\textstyle L\) is a power of two (e.g. 4,8,16,32..), this can be achieved by a simple binary shift right operation.

Is it an IIR or actually an FIR?

Upon initial inspection of the transfer function of Eqn. \(\small\textstyle\eqref{TF}\), it appears that the efficient MA filter is an IIR filter. However, analysing the pole-zero plot of the filter (shown on the right for \(\small\textstyle L=8\)), we see that the pole at DC has been cancelled by a zero, and that the resulting filter is actually an FIR filter, with the same result as Eqn. \(\small\textstyle\eqref{FIRdef}\).

Notice also that the frequency spacing of the zeros (corresponding to the nulls in the frequency response) are at spaced at \(\small\textstyle\pm\frac{Fs}{L}\). This can be readily seen for this example, where an MA of length 8, sampled at \(\small\textstyle 500Hz\), results in a \(\small\textstyle\pm62.5Hz\) resolution.

As a final point, notice that the our efficient filter requires a delay line of length \(\small\textstyle L+1\), compared with the FIR delay line of length, \(\small\textstyle L\). However, this is a small price to pay for the computation advantage of a filter just requiring one addition and one subtraction. As such, the MA filter of Eqn. \(\small\textstyle\eqref{TF}\) presented herein is very attractive for very low power processors, such as the Arm Cortex-M0 that have been traditionally overlooked for DSP operations.

Implementation

The MA filter of Eqn. \(\small\textstyle\eqref{TF}\) may be implemented in ASN FilterScript as follows:

 
ClearH1;  // clear primary filter from cascade 
interface L = {2,32,2,4}; // interface variable definition 

Main() 
Num = {1,zeros(L-1),-1}; // define numerator coefficients 
Den = {1,-1}; // define denominator coefficients 
Gain = 1/L; // define gain 



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UI experience 2020 pack

After downloading the ASN Filter Designer, most people just want to play with the tool, in order to get a feeling of whether it works for them. But how do you get started with the ASN Filter Designer? Based on some great user feedback, ASNFD v4.4 now comes with the UI experience 2020 pack. This pack includes detailed coaching tips, an enhanced user experience and step-by-step instructions to get you started with your design.

A quick overview of the ASN Filter Designer v4.4 is given below, and we’re sure that you’ll agree that it’s an awesome tool for DSP IIR/FIR digital filter design!

The ASN Filter Designer has a fast, intuitive user interface. Interactively design, validate and deploy your digital filter within minutes rather than hours. However, getting started with DSP Filter Design can be difficult, especially when you don’t have deep knowledge of digital signal processing. Most people just want to experiment with a tool to get a feeling whether it works for them (sure, there are tutorials and videos). But where do you start?

Start experimenting with filter design immediately

That’s why we have developed the UI Experience 2020 pack. Based on user feedback, we’ve created detailed tooltips and animations of key functionality. Within minutes, you’ll get a kick-start into functionalities such as chart zooming, panning and design markers.

Coaching tips, enhanced user experience, step-by-step instructions

Based on user feedback, the UI Experience 2020 pack includes:

  • Extensive coaching tips
  • Detailed explanations of design methods and types of filters
  • Enhanced user experience:
    • cursors
    • animations
    • visual effects
  • Short cuts to detailed worked solutions, tutorials and step-by-step instructions

Feedback from the user community has been very positive indeed! By providing detailed tooltips and animations of key functionality, the initial hurdle of designing a filter with your desired specifications has now been significantly simplified.

So start with the ASN Filter Designer right away, and cut your development costs by up to 75%!

ASN Filter Designer box
ASN Filter Designer box, the powerful DSP Filter Designer platform
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For many IoT sensor measurement applications, an IIR or FIR filter is just one of the many components needed for an algorithm. This could be a powerline interference canceller for a biomedical application or even a simpler DC loadcell filter. In many cases, it is necessary to integrate a filter into a complete algorithm in another domain.

Python is a very popular general-purpose programming language with support for numerical computing, allowing for the design of algorithms and performing data analysis. The language’s numpy and signal add-on modules attempt to bridge the gap between numerical algorithmic languages, such as Matlab and more traditional programming languages, such as C/C++. As such, it is much more appealing to experienced programmers, who are used to C/C++ data types, syntax and functionality, rather than Matlab’s scripting language that is more aimed at mathematicans developing algorithmic concepts.

ASN Filter Designer automatic code generator for Python

The ASN Filter Designer greatly simplifies exporting a designed filter to Python via its automatic code generator. The code generator supports all aspects of the ASN Filter Designer, allowing for a complete design comprised of H1, H2 and H3 filters and math operators to be fully integrated with an algorithm in Python.

The Python code generator can be accessed via the filter summary options (as shown on the right). Selecting this option will automatically generate a Python .py file based on the current design settings.

In order to use the generated code in a Python project, the following two framework files are provided in the
ASN Filter Designer’s installation directory in the \Python directory:

ASNFDFilterData.py
ASNFDImport.py

A convenient shortcut to the relevant Framework files and examples is available in the Filter summary toolbar via the folder symbol (see left).

Using the two framework files, you may build a demo of your choice based on the exported filter(s) specifications. The framework supports both Real and Complex filters in floating point only, and is built on ASN IP blocks, rather than Python’s signal module, which was seen to struggle with managing complex data. Thus, in order to expedite algorithm development with the framework, the following three demos are provided:

ASNFDPythonDemo: main demo file with various examples
RMSmeterDemo: An RMS amplitude powerline meter demo
EMGDataDemo: An EMG biomedical demo with a HPF, 50Hz notch filter and averaging

These framework files require the following Python dependency modules:

matplotlib.pyplot
numpy

An example of the generated code for use with the ASNFD-Python framework is shown below.

As seen, it is as simple as copying and pasting the filter coefficients from the ASN Filter Designer’s filter summary into a Python project script.

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Drones and DC motor control – How the ASN Filter Designer can save you a lot of time and effort

Drones are one of the golden nuggets in IoT. No wonder, they can play a pivotal role in congested cities and far away areas for delivery. Further, they can be a great help to give an overview of a large area or places which are difficult or dangerous to reach. However, most of the technology is still in its experimental stage.

Because drones have a lot of sensors, Advanced Solutions Nederland did some research on how drone producing companies have solved questions regarding their sensor technology, especially regarding DC motor control.

Until now: solutions developed with great difficulty

We found out that most producers spend weeks or even months on finding solutions for their sensor technology challenges. With the ASN Filter Designer, he/she could have come to a solution within days or maybe even hours. Besides, we expect that the measurement would be better too.

The biggest time coster is that until now algorithms were developed by handwork, i.e. they were developed in a lab environment and then tested in real-life. With the result of the test, the algorithm would be tweaked again until the desired results were reached. However, yet another challenge stems from the fact that a lab environment is where testing conditions are stable, so it’s very hard to make models work in real life. These steps result in rounds and rounds of ‘lab development’ and ‘real life testing’ in order to make any progress -which isn’t ideal!

How the ASN Filter Designer can help save a lot of time and effort

The ASN Filter Designer can help a lot of time in the design and testing of algorithms in the following ways:

  • Design, analyse and implement filters for drone sensor applications with real-time feedback and our powerful signal analyser.
  • Design filters for speed and positioning control for sensorless BLDC (brushless DC) motor applications.
  • Speed up deployment to Arm Cortex-M embedded processors.

 

Real-time feedback and powerful signal analyser

One of the key benefits of the ASN Filter Designer and signal analyser is that it gives real-time feedback. Once an algorithm is developed, it can easily be tested on real-life data. To analyse the real-life data, the ASN Filter Designer has a powerful signal analyser in place.

Design and analyse filters the easy way

You can easily design, analyse and implement filters for a variety of drone sensor applications, including: loadcells, strain gauges, torque, pressure, temperature, vibration, and ultrasonic sensors and assess their dynamic performance in real-time for a variety of input conditions.  With the ASN Filter Designer, you don’t have do to any coding yourself or break your head with specifications: you just have to draw the filter magnitude specification and the tool will calculate the coefficients itself.

Speed up deployment

Perform detailed time/frequency analysis on captured test datasets and fine-tune your design. Our Arm CMSIS-DSP and C/C++ code generators and software frameworks speed up deployment to a DSP, FPGA or micro-controller.

An example: designing BLDC motor control algorithms

BLDC (brushless DC) BLDC motors have found use in a variety of application areas, including: robotics, drones and cars. They have significant advantages over brushed DC motors and induction motors, such as: better speed-torque characteristics, high reliability, longer operating life, noiseless operation, and reduction of electromagnetic interference (EMI).

One advantage of BLDC motor control compared to standard DC motors is that the motor’s speed can be controlled very accurately using six-step commutation, making it a good choice for precision motion applications, such as robotics and drones.

Sensorless back-EMF and digital filtering

For most applications, monitoring of the back-EMF (back-electromotive force) signal of the unexcited phase winding is easier said than done, since it has significant noise distortion from PWM (pulse width modulation) commutation from the other energised windings. The  coupling  between  the  motor parameters, especially inductances, can induce ripple in the back-EMF signal that is synchronous with the PWM commutation.  As a consequence, this induced ripple on the back EMF signal leads to faulty commutation. Thus, the measurement challenge is how to accurately measure the zero-crossings of the back-EMF signal in the presence of PWM signals?

A standard solution is to use digital filtering, i.e. IIR, FIR or even a median (majority) filter. However, the challenge for most designers is how to find the best filter type and optimal filter specification for the motor under consideration.

The solution

The ASN Filter Designer allows engineers to work on speed and position sensorless BLDC motor control applications based on back-EMF filtering to easily experiment and see the filtering results on captured test datasets in real-time for various IIR, FIR and median (majority filtering) digital filtering schemes. The tool’s signal analyser implements a robust zero-crossings detector, allowing engineers to evaluate and fine-tune a complete sensorless BLDC control algorithm quickly and simply.

So, if you have a measurement problem, ask yourself:

Can I save time and money, and reduce the headache of design and implementation with an investment in new tooling?

Our licensing solutions start from just 125 EUR for a 3-month licence.

Find out what we can do for you, and learn more by visiting the ASN Filter Designer’s product homepage.

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The moving average (MA) filter is perhaps one of the most widely used FIR filters due to its conceptual simplicity and ease of implementation. As seen in the diagram below, notice that the filter doesn’t require any multiplications, just additions and a delay line, making it very suitable for many extreme low-power embedded devices with basic computational capabilities.

However, despite its simplicity, the moving average filter is optimal for reducing random noise while retaining a sharp step response, making it a versatile building block for smart sensor signal processing applications.

A moving average filter of length \(L\) for an input signal \(x(n)\) may be defined as follows:

\(y(n)=\large{\frac{1}{L}}\normalsize{\sum\limits_{k=0}^{L-1}x(n-k)}\) for \(\normalsize{n=0,1,2,3….}\)

Where, a simple rule of thumb states that the amount of noise reduction is equal to the square-root of the number of points in the average. For example, an MA of length 9 will result in a factor 3 noise reduction.

Frequency response of an MA filter of length 9. Notice the poor stopband attentuation at around -20dB.

Advantages

  • Most commonly used digital lowpass filter.
  • Optimal for reducing random noise while retaining a sharp step response.
  • Good smoother (time domain).
  • Unity valued filter coefficients, no MAC (multiply and accumulate) operations required.
  • Conceptually simple to implement.

Disadvantages

  • Inflexible frequency response: nudging a conjugate zero pair results in non-unity coefficients.
  • Poor lowpass filter (frequency domain): slow roll-off and terrible stopband attenuation characteristics.

Implementation

The MA filter may be implemented in ASN FilterScript as follows:

ClearH1;  // clear primary filter from cascade

Main()
Hd=movaver(8,"symbolic");  // design an 8th order MA 
Num = getnum(Hd);   // define numerator coefficients
Den = {1};          // define denominator coefficients
Gain = getgain(Hd); // define gain

A more computationally efficient implementation of the MA filter is discussed here.

Further reading

  • Understanding Digital Signal Processing, Chapter 5, R. G. Lyons
  • The Scientist and Engineer’s Guide to Digital Signal Processing, Chapter 15, Steven W. Smith

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